MC68HC08AS32 Datasheet, PDF (179/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.5 IRQ Pin
External Interrupt (IRQ)
IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODE set, both of the following actions must
occur to clear the IRQ latch:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK bit can also
prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge on IRQ
that occurs after writing to the ACK bit latches another interrupt
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
External Interrupt (IRQ)
Advance Information
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