MC68HC08AS32 Datasheet, PDF (195/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Input/Output (I/O) Ports
Port D
NOTE:
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the ADC. However, the DDRD bits
always determine whether reading port D returns the states of the
latches or logic 0.
TCLK — Timer Clock Input Bit
The PTD6/ATD14/TCLK pin is the external clock input for the TIM.
The prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK as the
TIM clock input. (See 16.9.1 TIM Status and Control Register.)
When not selected as the TIM clock, PTD6/ATD14/TCLK is available
for general-purpose I/O or as an ADC channel.
NOTE: Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
15.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read: 0
Write: 0
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Reset: 0
0
0
0
0
0
0
Figure 15-11. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[6:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Input/Output (I/O) Ports
Advance Information
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