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MC68HC08AS32 Datasheet, PDF (312/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)
Analog-to-Digital Converter (ADC)
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
NOTE: Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
19.4.2 Voltage Conversion
NOTE:
When the input voltage to the ADC equals VREFH (see 21.7 ADC
Characteristics), the ADC converts the signal to $FF (full scale). If the
input voltage equals VSSA/VREFL the ADC converts it to $00. Input
voltages between VREFH and VSSA/VREFL are a straight-line linear
conversion. All other input voltages will result in $FF if greater than
VREFH and $00 if less than VSSA/VREFL.
Input voltage should not exceed the analog supply voltages.
19.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16 µs to
complete. But since the ADC can run almost completely asynchronously
to the bus clock, (for example, the ADC is configured to derive its internal
clock from CGMXCLK and the bus clock is being derived from the PLL
within the CGM [CGMOUT]), this 16-µs conversion can take up to 17 µs
to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing
the conversion to wait until the next rising edge of the ADC internal clock.
With a 1-MHz ADC internal clock, the maximum sample rate is 59 kHz
to 62 kHz. Refer to 21.7 ADC Characteristics
Conversion Time = 16to17ADC Clock Cycles
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
Advance Information
312
Analog-to-Digital Converter (ADC)
MC68HC08AS32 — Rev. 3.0
MOTOROLA