MC68HC08AS32 Datasheet, PDF (364/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
from going onto the J1850 bus from a corrupted message.
20.7.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 20-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 20-6.
Advance Information
364
Byte Data Link Controller-Digital (BDLC-D)
MC68HC08AS32 — Rev. 3.0
MOTOROLA