MC68HC08AS32 Datasheet, PDF (130/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

System Integration Module (SIM)
9.4.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
MOR register is at logic 0. (See Section 13. Computer Operating
Properly (COP).)
9.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
NOTE: A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode
(stop instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the MOR register is logic 0, the SIM treats
the STOP instruction as an illegal opcode and causes an illegal opcode
reset.
9.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the V_DD voltage falls to the V_LVIF voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWR
and LVIRST bits in the CONFIG register are at logic 1. The RST pin will
be held low until the SIM counts 4096 CGMXCLK cycles after V_DD rises
above V_LVIR. Another 64 CGMXCLK cycles later, the CPU is released
from reset to allow the reset vector sequence to occur. (See Section 10.
Low-Voltage Inhibit (LVI).)
Advance Information
130
System Integration Module (SIM)
MC68HC08AS32 — Rev. 3.0
MOTOROLA