MC68HC08AS32 Datasheet, PDF (146/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Low-Voltage Inhibit (LVI)
10.3 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of V_DD pin level
10.4 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V_DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V_DD falls below a voltage, V_LVIF , and remains at or below
that level for nine or more consecutive CPU cycles. LVISTOP, enables
the LVI module during stop mode. This will ensure when the STOP
instruction is implemented, the LVI will continue to monitor the voltage
level on V_DD. LVIPWR, LVISTOP, and LVIRST are in the MOR register
($001F) (see Section 5. Mask Options). Once an LVI reset occurs, the
MCU remains in reset until V_DD rises above a voltage, V_LVIR. The output
of the comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
Advance Information
146
Low-Voltage Inhibit (LVI)
MC68HC08AS32 — Rev. 3.0
MOTOROLA