MC68HC08AS32 Datasheet, PDF (336/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period
64 µs in length, or
– A passive-to-active transition followed by an active period
128 µs in length
See Figure 20-6(a).
ACTIVE
PASSIVE
128 µs
OR
(A) LOGIC 0
64 µs
ACTIVE
PASSIVE
128 µs
OR
(B) LOGIC 1
64 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
≥ 240 µs
(C) BREAK
200 µs
(D) START OF FRAME
200 µs
(E) END OF DATA
280 µs
300 µs
20 µs
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 20-6. J1850 VPW Symbols with Nominal Symbol Times
Advance Information
336
Byte Data Link Controller-Digital (BDLC-D)
MC68HC08AS32 — Rev. 3.0
MOTOROLA