MC68HC08AS32 Datasheet, PDF (222/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Timer Interface (TIM)
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
R
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
R = Reserved
Figure 16-3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. Also when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until
the TSTOP bit is cleared.
Advance Information
222
Timer Interface (TIM)
MC68HC08AS32 — Rev. 3.0
MOTOROLA