MC68HC08AS32 Datasheet, PDF (343/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
20.5.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and will continue with each bit thereafter.
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
that is simultaneously transmitted. Hence, logic 0s are said to be
dominant and logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, the node loses arbitration and immediately stops
transmitting. This is known as bitwise arbitration.
ACTIVE
TRANSMITTER A
PASSIVE
ACTIVE
TRANSMITTER B
PASSIVE
ACTIVE
J1850 BUS
PASSIVE
0
1
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
1
1
0
0
0
1
1
0
0
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
DATA DATA DATA
DATA DATA
SOF
BIT 1 BIT 2 BIT 3
BIT 4 BIT 5
Figure 20-11. J1850 VPW Bitwise Arbitrations
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
343