MC68HC08AS32 Datasheet, PDF (148/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Low-Voltage Inhibit (LVI)
10.4.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V_DD must
remain at or below the V_LVIF level for nine or more consecutive CPU
cycles. V_DD must be above V_LVIR for only one CPU cycle to bring the
MCU out of reset.
10.5 LVI Status Register
The LVI status register flags V_DD voltages below the V_LVIF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_LVIF voltage or 32 to 40 CGMXCLK cycles. (See Table 10-2.) Reset
clears the LVIOUT bit.
Table 10-2. LVIOUT Bit Indication
V_DD
At Level:
For Number of
CGMXCLK Cycles:
V_DD > V_LVIR
V_DD < V_LVIF
V_DD < V_LVIF
Any
< 32 CGMXCLK Cycles
Between 32 and 40
CGMXCLK Cycles
V_DD < V_LVIF
V_LVIF < V_DD < V_LVIR
> 40 CGMXCLK Cycles
Any
LVIOUT
0
0
0 or 1
1
Previous Value
Advance Information
148
Low-Voltage Inhibit (LVI)
MC68HC08AS32 — Rev. 3.0
MOTOROLA