MC68HC08AS32 Datasheet, PDF (357/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
20.7.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ALOOP DLOOP RX4XE
Write:
NBFS
TEOD
TSIFR TMIFR1 TMIFR0
Reset: 1
1
0
0
0
0
0
0
Figure 20-17. BDLC Control Register 2 (BCR2)
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the
user clears ALOOP, to indicate that the off-chip analog transceiver is
no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is
looped back to the BDLC receiver. The J1850 bus is not
driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (t_TRV4) before message reception or
a minimum of inter-frame symbol time (t_TRV6) before message
transmission. (See 21.16 BDLC Receiver VPW Symbol
Timings.)
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
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