MC68HC08AS32 Datasheet, PDF (22/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

List of Figures
Advance Information
22
Figure
Title
Page
16-7
16-8
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
TIM Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . . .232
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .238
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .247
Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .250
SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .258
SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .261
SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .264
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .265
Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .268
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .269
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .270
SCI BAUD Rate Register 1 (SCBR) . . . . . . . . . . . . . . . . . .271
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .279
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .280
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .283
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .285
Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . .287
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . .289
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . .290
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .293
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .294
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .302
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .305
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .308
19-1
19-2
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
ADC Status and Control Register (ADSCR). . . . . . . . . . . .315
List of Figures
MC68HC08AS32 — Rev. 3.0
MOTOROLA