PIC18F45K80-I Datasheet, PDF (92/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
PIE5
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
EEADRH
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- --00
---- --00
---- --00
EEADR
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
EEDATA
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
ECANCON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 0000
0001 0000
uuuu uuuu
COMSTAT
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
CIOCON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0
0000 ---0
uuuu ---u
CANCON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000
1000 0000
uuuu uuuu
CANSTAT
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000
1000 0000
uuuu uuuu
RXB0D7
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D6
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D5
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D4
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D3
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D2
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D1
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D0
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0DLC
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0EIDL
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0EIDH
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0SIDL
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx
uuuu u-uu
uuuu u-uu
RXB0SIDH
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0CON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
CM1CON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111
0001 1111
uuuu uuuu
CM2CON
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111
0001 1111
uuuu uuuu
ANCON0
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111
1111 1111
uuuu uuuu
ANCON1
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -111 1111
-111 1111
-uuu uuuu
WPUB
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx
1111 1111
uuuu uuuu
IOCB
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ----
0000 ----
uuuu ----
PMD0
PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
2:
3:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 5-3 for Reset value for specific conditions.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS39977F-page 92
 2010-2012 Microchip Technology Inc.