PIC18F45K80-I Datasheet, PDF (418/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 27-31: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS,
LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 1]⁽¹⁾
R/W-x
EID7
bit 7
R/W-x
EID6
R/W-x
EID5
R/W-x
FEID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 27-32: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN RECEIVE MODE
[0  n  5, 0  m  7, TXnEN (BSEL<n>) = 0]⁽¹⁾
R-x
BnDm7
bit 7
R-x
BnDm6
R-x
BnDm5
R-x
BnDm4
R-x
BnDm3
R-x
BnDm2
R-x
BnDm1
R-x
BnDm0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to
B0D7.
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 27-33: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN TRANSMIT MODE
[0  n  5, 0  m  7, TXnEN (BSEL<n>) = 1]⁽¹⁾
R/W-x
BnDm7
bit 7
R/W-x
BnDm6
R/W-x
BnDm5
R/W-x
BnDm4
R/W-x
BnDm3
R/W-x
BnDm2
R/W-x
BnDm1
R/W-x
BnDm0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
Note 1: These registers are available in Mode 1 and 2 only.
DS39977F-page 418
 2010-2012 Microchip Technology Inc.