PIC18F45K80-I Datasheet, PDF (229/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
16.5.2
TIMER3 GATE SOURCE
SELECTION
The Timer3 gate source can be selected from one of
four different sources. Source selection is controlled by
the T3GSS<1:0> bits (T3GCON<1:0>). The polarity for
each available source is also selectable and is
controlled by the T3GPOL bit (T3GCON<6>).
TABLE 16-2: TIMER3 GATE SOURCES
T3GSS<1:0>
Timer3 Gate Source
00
Timerx Gate Pin
01
TMR4 to Match PR4
(TMR4 increments to match PR4)
10
Comparator 1 Output
(comparator logic high output)
11
Comparator 2 Output
(comparator logic high output)
16.5.2.1 T3G Pin Gate Operation
The T3G pin is one source for Timer3 gate control. It can
be used to supply an external source to the Timerx gate
circuitry.
16.5.2.2 Timer4 Match Gate Operation
The TMR4 register will increment until it matches the
value in the PR4 register. On the very next increment
cycle, TMR4 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on T3GPOL, Timerx increments differently
when TMR4 matches PR4. When T3GPOL = 1, Timer3
increments for a single instruction cycle following a
TMR4 match with PR4. When T3GPOL = 0, Timer3
increments continuously, except for the cycle following
the match, when the gate signal goes from low-to-high.
16.5.2.3 Comparator 1 Output Gate
Operation
The output of Comparator 1 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer3 will
increment depending on the transitions of the
CMP1OUT (CMSTAT<6>) bit.
16.5.2.4 Comparator 2 Output Gate
Operation
The output of Comparator 2 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer3 will
increment depending on the transitions of the
CMP2OUT (CMSTAT<7>) bit.
16.5.3 TIMER3 GATE TOGGLE MODE
When Timer3 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3
gate signal, as opposed to the duration of a single level
pulse.
The Timer3 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 16-3.)
The T3GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3 Gate Toggle mode is enabled by setting the
T3GTM bit (T3GCON<5>). When the T3GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
FIGURE 16-3:
TMR3GE
T3GPOL
T3GTM
T3G_IN
TIMER3 GATE TOGGLE MODE
T3CKI
T3GVAL
Timer3
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
 2010-2012 Microchip Technology Inc.
DS39977F-page 229