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| PIC18F45K80-I Datasheet, PDF (395/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology | |||
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PIC18F66K80 FAMILY
REGISTER 27-2: CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
R-0
R-0
R-0
R-0
U-0
Mode 0
OPMODE2(1) OPMODE1(1) OPMODE0(1)
â
ICODE2 ICODE1 ICODE0
â
Mode 1,2
R-1
R-0
R-0
R-0
R-0
OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3
bit 7
R-0
EICODE2
R-0
EICODE1
R-0
EICODE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
bit 3-1,4-0
bit 0
bit 4-0
OPMODE<2:0>: Operation Mode Status bits(1)
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
Mode 0:
Unimplemented: Read as â0â
Mode 0:
ICODE<2:0>: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code
indicates the source of the interrupt. By copying ICODE<3:1> to WIN<3:0> (Mode 0) or EICODE<4:0>
to EWIN<4:0> (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area.
See Example 27-2 for a code example. To simplify the description, the following table lists all five bits.
No interrupt
CAN bus error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
RXB0 interrupt
RXB1 interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B5 interrupt
Mode 0
00000
00010
00100
00110
01000
01010
01100
00010
-----
-----
-----
-----
-----
-----
-----
-----
Mode 1
00000
00010
00100
00110
01000
10001
10000
01110
10000
10001
10010
10011
10100
10101
10110
10111
Mode 2
00000
00010
00100
00110
01000
-----
10000
01110
10000
10000
10010(2)
10011(2)
10100(2)
10101(2)
10110(2)
10111(2)
Mode 0:
Unimplemented: Read as â0â
Mode 1, 2:
EICODE<4:0>: Interrupt Code bits
See ICODE<3:1> above.
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch the CAN module in
Disable/Sleep mode before putting the device to Sleep.
2: If the buffer is configured as a receiver, the EICODE bits will contain â10000â upon interrupt.
ï£ 2010-2012 Microchip Technology Inc.
DS39977F-page 395
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