PIC18F45K80-I Datasheet, PDF (231/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 16-5:
TMR3GE
T3GPOL
T3GSPM
T3GTM
T3GGO/
T3DONE
T3G_IN
TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
Set by Software
Counting Enabled on
Rising Edge of T3G
Cleared by Hardware on
Falling Edge of T3GVAL
T3CKI
T3GVAL
Timer3
TMR3GIF
N
Cleared by Software
N+1
N+2
N+3
Set by Hardware on
Falling Edge of T3GVAL
N+4
Cleared by
Software
16.5.5 TIMER3 GATE VALUE STATUS
When Timer3 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T3GVAL bit (T3GCON<2>).
The T3GVAL bit is valid even when the Timer3 gate is
not enabled (TMR3GE bit is cleared).
16.5.6 TIMER3 GATE EVENT INTERRUPT
When the Timer3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T3GVAL
occurs, the TMR3GIF flag bit in the PIR2 register will be
set. If the TMR3GIE bit in the PIE2 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
 2010-2012 Microchip Technology Inc.
DS39977F-page 231