PIC18F45K80-I Datasheet, PDF (60/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
3.6 Internal Oscillator Block
The PIC18F66K80 family of devices includes an internal
oscillator block which generates two different clock
signals. Either clock can be used as the microcontroller’s
clock source, which may eliminate the need for an
external oscillator circuit on the OSC1 and/or OSC2 pins.
The Internal oscillator consists of three blocks,
depending on the frequency of operation. They are
HF-INTOSC, MF-INTOSC and LF-INTOSC.
In HF-INTOSC mode, the internal oscillator can provide
a frequency ranging from 31 KHz to 16 MHz, with the
postscaler deciding the selected frequency
(IRCF<2:0>).
The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit
(OSCCON2<0>) also decide which INTOSC provides
the lower frequency (500 kHz to 31 KHz). For the
HF-INTOSC to provide these frequencies, INTSRC = 1
and MFIOSEL = 0.
In HF-INTOSC, the postscaler (IRCF<2:0>) provides
the frequency range of 31 kHz to 16 MHz. If
HF-INTOSC is used with the PLL, the input frequency
to the PLL should be 4 MHz to 16 MHz
(IRCF<2:0> = 111, 110 or 101).
For MF-INTOSC mode to provide a frequency range of
500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1.
The postscaler (IRCF<2:0>), in this mode, provides the
frequency range of 31 kHz to 500 kHz.
The LF-INTOSC can provide only 31 kHz if INTSRC = 0.
The LF-INTOSC provides 31 kHz and is enabled if it is
selected as the device clock source. The mode is
enabled automatically when any of the following are
enabled:
• Power-up Timer (PWRT)
• Fail-Safe Clock Monitor (FSCM)
• Watchdog Timer (WDT)
• Two-Speed Start-up
These features are discussed in greater detail in
Section 28.0 “Special Features of the CPU”.
The clock source frequency (HF-INTOSC, MF-INTOSC
or LF-INTOSC direct) is selected by configuring the
IRCFx bits of the OSCCON register, as well the
INTSRC and MFIOSEL bits. The default frequency on
device Resets is 8 MHz.
3.6.1 INTIO MODES
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSCx Configuration bits, are available:
• In INTIO1 mode, the OSC2 pin (RA6) outputs
FOSC/4, while OSC1 functions as RA7 (see
Figure 3-8) for digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-9). Both
are available as digital input and output ports.
FIGURE 3-8: INTIO1 OSCILLATOR MODE
RA7
FOSC/4
I/O (OSC1)
PIC18F66K80
OSC2
FIGURE 3-9: INTIO2 OSCILLATOR MODE
RA7
I/O (OSC1)
PIC18F66K80
RA6
I/O (OSC2)
3.6.2 INTPLL MODES
The 4x Phase Lock Loop (PLL) can be used with the
HF-INTOSC to produce faster device clock speeds
than are normally possible with the internal oscillator
sources. When enabled, the PLL produces a clock
speed of 16 MHz or 64 MHz.
PLL operation is controlled through software. The
control bits, PLLEN (OSCTUNE<6>) and PLLCFG
(CONFIG1H<4>), are used to enable or disable its
operation. The PLL is available only to HF-INTOSC.
The other oscillator is set with HS and EC modes. Addi-
tionally, the PLL will only function when the selected
output frequency is either 4 MHz or 16 MHz
(OSCCON<6:4> = 111, 110 or 101).
Like the INTIO modes, there are two distinct INTPLL
modes available:
• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (see Figure 3-8).
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2 (see
Figure 3-9).
DS39977F-page 60
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