PIC18F45K80-I Datasheet, PDF (479/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
28.6 Program Verification and
Code Protection
The user program memory is divided into four blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into blocks on
binary boundaries.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 28-6 shows the program memory organization for
48, 64, 96 and 128 Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 28-4.
FIGURE 28-6:
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F66K80 FAMILY
000000h
Code Memory
01FFFFh
Unimplemented
Read as ‘0’
200000h
Configuration
and ID
Space
Device/Memory Size⁽¹⁾
PIC18FX6K80
PIC18FX5K80
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Address
Boot Block Boot Block Boot Block Boot Block 0000h
2 kW
Block 0
2 kW
Block 0 0800h
Block 0
7 kW
Block 0
3 kW _1000h
6 kW
2 kW
1FFFh
Block 1
4 kW
Block 1 2000h
4 kW 3FFFh
Block 1
8 kW
Block 1
8 kW
Block 2
4 kW
Block 2 4000h
4 kW 5FFFh
Block 3
4 kW
Block 3 6000h
4 kW 7FFFh
Block 2
8 kW
Block 2
8 kW
8000h
BFFFh
Block 3
8 kW
Block 3
8 kW
C000h
FFFFh
10000h
13FFFh
14000h
17FFFh
18000h
1BFFFh
1C000h
1FFFFh
3FFFFFh
Note 1: Sizes of memory areas are not to scale.
2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
 2010-2012 Microchip Technology Inc.
DS39977F-page 479