PIC18F45K80-I Datasheet, PDF (268/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
In addition to the expanded range of modes available
through the CCP1CON and ECCP1AS registers, the
ECCP module has two additional registers associated
with Enhanced PWM operation and auto-shutdown
features. They are:
• ECCP1DEL – Enhanced PWM Control
• PSTR1CON – Pulse Steering Control
20.1 ECCP Outputs and Configuration
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
The CCP1CON register is modified to allow control
over four PWM outputs: ECCP1/P1A, P1B, P1C and
P1D. Applications can use one, two or four of these
outputs.
The outputs that are active depend on the ECCP
operating mode selected. The pin assignments are
summarized in Table 20-2.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRIS direction
bits for the port pins must also be set as outputs.
20.1.1
ECCP MODULE AND TIMER
RESOURCES
The ECCP modules use Timers, 1, 2, 3 and 4, depend-
ing on the mode selected. These timers are available to
CCP modules in Capture, Compare or PWM modes, as
shown in Table 20-1.
TABLE 20-1:
ECCP Mode
Capture
Compare
PWM
ECCP MODE – TIMER
RESOURCE
Timer Resource
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer to ECCP enable bits in the
CCPTMRS register (Register 20-2). The interactions
between the two modules are depicted in Figure 20-1.
Capture operations are designed to be used when the
timer is configured for Synchronous Counter mode.
Capture operations may not work as expected if the
associated timer is configured for Asynchronous Counter
mode.
20.2 Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
ECCP1 pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every fourth rising edge
• Every 16^th rising edge
The event is selected by the mode select bits,
CCP1M<3:0> (CCP1CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP1IF, is set
(PIR3<1>). The flag must be cleared by software. If
another capture occurs before the value in the
CCPR1H/L register is read, the old captured value is
overwritten by the new captured value.
20.2.1 ECCP PIN CONFIGURATION
In Capture mode, the appropriate ECCP1 pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If the ECCP1 pin is configured as an out-
put, a write to the port can cause a capture
condition.
DS39977F-page 268
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