PIC18F45K80-I Datasheet, PDF (214/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
14.4 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits at once to both the high and low bytes of Timer1.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
14.5 SOSC Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, SOSCI (input) and SOSCO (amplifier
output). It can be enabled one of these ways:
• Setting the SOSCEN bit in either the T1CON or
T3CON register (TxCON<3>)
• Setting the SOSCGO bit in the OSCCON2 register
(OSCCON2<3>)
• Setting the SCSx bits to secondary clock source in
the OSCCON register (OSCCON<1:0> = 01)
The SOSCGO bit is used to warm up the SOSC so that
it is ready before any peripheral requests it.
The oscillator is a low-power circuit rated for 32 kHz
crystals. It will continue to run during all power-
managed modes. The circuit for a typical low-power
oscillator is depicted in Figure 14-2. Table 14-2
provides the capacitor selection for the SOSC
oscillator.
The user must provide a software time delay to ensure
proper start-up of the SOSC oscillator.
FIGURE 14-2:
C1
12 pF
EXTERNAL COMPONENTS
FOR THE SOSC
OSCILLATOR
PIC18F66K80
SOSCI
XTAL
32.768 kHz
C2
12 pF
SOSCO
Note:
See the Notes with Table 14-2 for additional
information about capacitor selection.
TABLE 14-2:
CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR^(2,3,4,5)
Oscillator
Type
Freq.
C1
C2
LP
32 kHz
12 pF⁽¹⁾
12 pF⁽¹⁾
Note 1:
2:
3:
4:
5:
Microchip suggests these values as a starting
point in validating the oscillator circuit.
Higher capacitance increases the stability of
the oscillator, but also increases the start-up
time.
Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate
values of external components.
Capacitor values are for design guidance only.
Values listed would be typical of a CL = 10 pF
rated crystal, when SOSCSEL<1:0> = 11.
Incorrect capacitance value may result in a fre-
quency not meeting the crystal manufacturer’s
tolerance specification.
The SOSC crystal oscillator drive level is determined
based on the SOSCSELx (CONFIG1L<4:3>) Configu-
ration bits. The Higher Drive Level mode,
SOSCSEL<1:0> = 11, is intended to drive a wide
variety of 32.768 kHz crystals with a variety of Load
Capacitance (CL) ratings.
The Lower Drive Level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
correctly if excessively large discrete capacitors are
placed on the SOSCO and SOSCI pins. This mode is
designed to work only with discrete capacitances of
approximately 3 pF-10 pF on each pin.
Crystal manufacturers usually specify a CL (Load
Capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 14-2.
DS39977F-page 214
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