PIC18F45K80-I Datasheet, PDF (300/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 21-6: SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ SLAVE MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT ACKDT⁽¹⁾ ACKEN⁽¹⁾
RCEN⁽¹⁾
PEN⁽¹⁾
RSEN⁽¹⁾
bit 7
R/W-0
SEN⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1 = Enables interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address is disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)⁽¹⁾
1 = Not Acknowledged
0 = Acknowledged
bit 4
ACKEN: Acknowledge Sequence Enable bit⁽¹⁾
1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)⁽¹⁾
1 = Enables Receive mode for I²C™
0 = Receive is Idle
bit 2
PEN: Stop Condition Enable bit⁽¹⁾
1 = Initiates Stop condition on SDA and SCL pins; automatically cleared by hardware
0 = Stop condition is Idle
bit 1
RSEN: Repeated Start Condition Enable bit⁽¹⁾
1 = Initiates Repeated Start condition on SDA and SCL pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
bit 0
SEN: Stretch Enable bit⁽¹⁾
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I²C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
REGISTER 21-7: SSPMSK: I²C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)⁽¹⁾
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0⁽²⁾
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MSK<7:0>: Slave Address Mask Select bit⁽²⁾
1 = Masking of corresponding bit of SSPADD is enabled
0 = Masking of corresponding bit of SSPADD is disabled
Note 1: This register shares the same SFR address as SSPADD and is only addressable in select MSSP
operating modes. See Section 21.4.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
DS39977F-page 300
 2010-2012 Microchip Technology Inc.