PIC18F45K80-I Datasheet, PDF (572/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 31-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKPx = 0)
71
72
78
SCK
(CKP = 1)
80
79
SDO
MSb
bit 6 - - - - - - 1
SDI
Note:
75, 76
MSb In
74
73
bit 6 - - - - 1
Refer to Figure 31-3 for load conditions.
83
79
78
LSb
77
LSb In
TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS  to SCK  or SCK  Input
TSSL2SCL
3 TCY
—
70A TSSL2WB SS to write to SSPBUF
3 TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
20
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
—
75
TDOR
SDO Data Output Rise Time
—
25
76
TDOF
SDO Data Output Fall Time
—
25
77
TSSH2DOZ SS  to SDO Output High-impedance
10
50
78
TSCR
SCK Output Rise Time (Master mode)
—
25
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
—
50
83
TSCH2SSH, SS  after SCK Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
DS39977F-page 572
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