PIC18F45K80-I Datasheet, PDF (222/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
15.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides
the input for the four-bit output counter/postscaler. This
counter generates the TMR2 match interrupt flag, which
is latched in TMR2IF (PIR1<1>). The interrupt is enabled
by setting the TMR2 Match Interrupt Enable bit, TMR2IE
(PIE1<1>).
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 15-1:
TIMER2 BLOCK DIAGRAM
T2OUTPS<3:0>
T2CKPS<1:0>
FOSC/4
4
2
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
Reset
TMR2
8
15.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can optionally be used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 21.0
“Master Synchronous Serial Port (MSSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
PR2
8
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
PMD1
Legend:
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
PSPIF
ADIF
RC1IF
TX1IF
SSPIF TMR1GIF TMR2IF
PSPIE
ADIE
RC1IE
TX1IE
SSPIE TMR1GIE TMR2IE
PSPIP
ADIP
RC1IP
TX1IP
SSPIP TMR1GIP TMR2IP
Timer2 Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1
Timer2 Period Register
PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD
— = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
T2CKPS0
TMR0MD
DS39977F-page 222
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