PIC18F45K80-I Datasheet, PDF (270/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
20.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the ECCP1 pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the
interrupt flag bit, CCP1IF, is set.
20.3.1 ECCP PIN CONFIGURATION
Users must configure the ECCP1 pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP1CON register will force
the ECCP1 compare output latch
(depending on device configuration) to the
default low level. This is not the port I/O
data latch.
20.3.2 TIMER1/2/3/4 MODE SELECTION
Timer1, 2, 3 or 4 must be running in Timer mode or
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
20.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the ECCP1 pin is not affected;
only the CCP1IF interrupt flag is affected.
20.3.4 SPECIAL EVENT TRIGGER
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable Period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
FIGURE 20-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
0
TMR1H TMR1L
1
TMR3H TMR3L
C1TSEL0
C1TSEL1
C1TSEL2
Comparator
Compare
Match
CCPR1H CCPR1L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
Set CCP1IF
Output
Logic
SQ
R
4
CCP1CON<3:0>
ECCP1 Pin
TRIS
Output Enable
DS39977F-page 270
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