PIC18F45K80-I Datasheet, PDF (356/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
22.5.2
EUSARTx SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCxIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits (INTCON<7:6>) are set.
TABLE 22-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF TMR1GIF TMR2IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE TMR1GIE TMR2IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP TMR1GIP TMR2IP
PIR3
—
—
RC2IF
TX2IF CTMUIF CCP2IF CCP1IF
PIE3
—
—
RC2IE
TX2IE CTMUIE CCP2IE CCP1IE
IPR3
—
—
RC2IP
TX2IP CTMUIP CCP2IP CCP1IP
RCSTA1
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RCREG1
EUSART1 Receive Register
TXSTA1
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
BAUDCON1 ABDOVF RCIDL
RXDTP TXCKP BRG16
—
WUE
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
RCSTA2
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RCREG2
EUSART2 Receive Register
TXSTA2
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
BAUDCON2 ABDOVF RCIDL
RXDTP TXCKP BRG16
—
WUE
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
PMD0
CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD
ODCON
SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
—
—
—
RX9D
TX9D
ABDEN
RX9D
TX9D
ABDEN
SSPMD
U1OD
DS39977F-page 356
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