PIC18F45K80-I Datasheet, PDF (612/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
TRISC Register ......................................................... 181
PORTD
Associated Registers ................................................ 186
LATD Register .......................................................... 184
PORTD Register ....................................................... 184
TRISD Register ......................................................... 184
PORTE
Associated Registers ................................................ 188
LATE Register........................................................... 187
PORTE Register ....................................................... 187
RE0/AN5/RD Pin....................................................... 192
RE1/AN6/C1OUT/WR Pin......................................... 192
RE2/AN7/C2OUT/CS Pin.......................................... 192
TRISE Register ......................................................... 187
PORTF
Associated Registers ................................................ 189
LATF Register ........................................................... 189
PORTF Register ....................................................... 189
TRISF Register ......................................................... 189
PORTG
Associated Registers ................................................ 191
LATG Register .......................................................... 190
PORTG Register ....................................................... 190
TRISG Register......................................................... 190
Power-Managed Modes ...................................................... 65
and EUSART Operation............................................ 337
and PWM Operation ................................................. 285
and SPI Operation .................................................... 295
Clock Transitions and Status Indicators...................... 66
Entering....................................................................... 65
Exiting Idle and Sleep Modes ..................................... 76
by Interrupt.......................................................... 76
by Reset.............................................................. 76
by WDT Time-out................................................ 76
Without an Oscillator Start-up Delay................... 76
Idle Modes .................................................................. 70
PRI_IDLE ............................................................ 71
RC_IDLE............................................................. 72
SEC_IDLE........................................................... 71
Multiple Sleep Commands .......................................... 66
Run Modes.................................................................. 66
PRI_RUN ............................................................ 66
RC_RUN ............................................................. 67
SEC_RUN........................................................... 66
Selecting ..................................................................... 65
Sleep Mode ................................................................. 70
OSC1 and OSC2 Pin States ............................... 63
Summary (table) ......................................................... 65
Power-on Reset (POR) ....................................................... 81
Oscillator Start-up Timer (OST) .................................. 84
Power-up Timer (PWRT) ............................................ 83
Time-out Sequence..................................................... 84
Power-up Delays................................................................. 63
Power-up Timer (PWRT)............................................... 63, 83
Prescaler, Capture ............................................................ 258
Prescaler, Timer0.............................................................. 207
Prescaler, Timer2.............................................................. 263
PRI_IDLE Mode .................................................................. 71
PRI_RUN Mode .................................................................. 66
Program Counter (PC) ...................................................... 103
PCL, PCH and PCU Registers.................................. 103
PCLATH and PCLATU Registers ............................. 103
Program Memory
Code Protection ........................................................ 480
Extended Instruction Set ........................................... 125
DS39977F-page 612
Hard Memory Vectors............................................... 102
Instructions ............................................................... 107
Two-Word ......................................................... 107
Interrupt Vector ......................................................... 102
Look-up Tables ......................................................... 105
Memory Maps ........................................................... 101
Hard Vectors..................................................... 102
Reset Vector ............................................................. 102
Program Verification and Code Protection ....................... 479
Associated Registers ................................................ 480
Programming, Device Instructions.................................... 483
PSP.See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module).
PUSH................................................................................ 512
PUSH and POP Instructions............................................. 104
PUSHL.............................................................................. 528
PWM (CCP Module)
Associated Registers ................................................ 264
Duty Cycle ................................................................ 263
Example Frequencies/Resolutions ........................... 263
Period ....................................................................... 262
Setup for PWM Operation......................................... 263
TMR2 to PR2 Match ................................................. 262
PWM (ECCP Module)
Effects of a Reset ..................................................... 285
Operation in Power-Managed Modes ....................... 285
Operation with Fail-Safe Clock Monitor .................... 285
Pulse Steering Mode ................................................ 282
Steering Synchronization.......................................... 284
PWM Mode. See Enhanced Capture/Compare/PWM ...... 271
Q
Q Clock ............................................................................. 263
R
RAM. See Data Memory.
RC_IDLE Mode................................................................... 72
RC_RUN Mode................................................................... 67
RCALL .............................................................................. 513
RCON Register
Bit Status During Initialization ..................................... 87
Reader Response............................................................. 618
Receiver Warning ............................................................. 455
Reference Clock Output ..................................................... 61
Register File...................................................................... 110
Register File Summary ............................................. 113–121
Registers
ADCON0 (A/D Control 0).......................................... 358
ADCON1 (A/D Control 1).......................................... 359
ADCON2 (A/D Control 2).......................................... 360
ADRESH (A/D Result High Byte, Left Justified, ADFM =
0) ...................................................................... 362
ADRESH (A/D Result High Byte, Right Justified, ADFM
= 1) ................................................................... 362
ADRESL (A/D Result Low Byte, Left Justified, ADFM = 0)
362
ADRESL (A/D Result Low Byte, Right Justified, ADFM =
1) ...................................................................... 363
ANCON0 (A/D Port Configuration 0) ........................ 363
ANCON1 (A/D Port Configuration 1) ........................ 364
BAUDCONx (Baud Rate Control) ............................. 336
BIE0 (Buffer Interrupt Enable 0) ............................... 437
BnCON (TX/RX Buffer n Control, Receive Mode) .... 413
BnCON (TX/RX Buffer n Control, Transmit Mode) ... 414
BnDLC (TX/RX Buffer n Data Length Code in Receive
Mode) ............................................................... 419
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