PIC18F45K80-I Datasheet, PDF (57/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1/3/5/7 oscillator must be
enabled to select the secondary clock
source. The Timerx oscillator is enabled by
setting the SOSCEN bit in the Timerx Con-
trol register (TxCON<3>). If the Timerx
oscillator is not enabled, then any attempt
to select a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timerx
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timerx
oscillator starts.
3.3.2.1
System Clock Selection and Device
Resets
Since the SCSx bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC<3:0> Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock sources (HS, EC, XT, LP, External RC
and PLL-enabled modes).
In those cases when the internal oscillator block, with-
out PLL, is the default clock on Reset, the Fast RC
Oscillator (INTOSC) will be used as the device clock
source. It will initially start at 8 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF<2:0> bits (‘110’).
Regardless of which primary oscillator is selected,
INTOSC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSCx Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source or the internal
oscillator will have two bit setting options for the possible
values of the SCS<1:0> bits, at any given time.
3.3.3 OSCILLATOR TRANSITIONS
PIC18F66K80 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
3.4 RC Oscillator
For timing-insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The actual
oscillator frequency is a function of several factors:
• Supply voltage
• Values of the external resistor (REXT) and capacitor
(CEXT)
• Operating temperature
Given the same device, operating voltage and tempera-
ture, and component values, there will also be unit to unit
frequency variations. These are due to factors such as:
• Normal manufacturing variation
• Difference in lead frame capacitance between
package types (especially for low CEXT values)
• Variations within the tolerance of the limits of
REXT and CEXT
In the RC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-2 shows how the R/C combination is
connected.
FIGURE 3-2:
VDD
RC OSCILLATOR MODE
REXT
CEXT
OSC1
Internal
Clock
VSS
PIC18F66K80
OSC2/CLKO
FOSC/4
Recommended values: 3 k  REXT  100 k
20 pF CEXT  300 pF
The RCIO Oscillator mode (Figure 3-3) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-3:
VDD
RCIO OSCILLATOR MODE
REXT
CEXT
VSS
RA6
OSC1
Internal
Clock
PIC18F66K80
I/O (OSC2)
Recommended values: 3 k  REXT  100 k
20 pF CEXT  300 pF
 2010-2012 Microchip Technology Inc.
DS39977F-page 57