PIC18F45K80-I Datasheet, PDF (469/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 28-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
—
bit 7
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
—
—
—
EBTR3
EBTR2
EBTR1
EBTR0
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit
1 = Block 3 is not protected from table reads executed in other blocks⁽¹⁾
0 = Block 3 is protected from table reads executed in other blocks⁽¹⁾
EBTR2: Table Read Protection bit
1 = Block 2 is not protected from table reads executed in other blocks⁽¹⁾
0 = Block 2 is protected from table reads executed in other blocks⁽¹⁾
EBTR1: Table Read Protection bit
1 = Block 1 is not protected from table reads executed in other blocks⁽¹⁾
0 = Block 1 is protected from table reads executed in other blocks⁽¹⁾
EBTR0: Table Read Protection bit
1 = Block 0 is not protected from table reads executed in other blocks⁽¹⁾
0 = Block 0 is protected from table reads executed in other blocks⁽¹⁾
Note 1: For the memory size of the blocks, see Figure 28-6.
 2010-2012 Microchip Technology Inc.
DS39977F-page 469