PIC18F45K80-I Datasheet, PDF (364/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 23-9: ANCON1: A/D PORT CONFIGURATION REGISTER 1
U-1
—
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
ANSEL14⁽¹⁾ ANSEL13⁽¹⁾ ANSEL12⁽¹⁾ ANSEL11⁽¹⁾
R/W-1
ANSEL10
R/W-1
ANSEL9
R/W-1
ANSEL8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
ANSEL14: RD3/C2INB Pin Analog Enable bit⁽¹⁾
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
ANSEL13: RD2/C2INA Pin Analog Enable bit⁽¹⁾
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
ANSEL12: RD1/C1INB Pin Analog Enable bit⁽¹⁾
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
ANSEL11: RD0/C1INA Pin Analog Enable bit⁽¹⁾
1 = Pin is configured as an analog channel: digital input disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
ANSEL11<10:8>: Analog Port Configuration bits (AN10 through AN8)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin configured as a digital port
Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS) or the voltage level on the
RA3/VREF+/AN3 and RA2/VREF-/AN2 pins. VREF+ has
two additional internal voltage reference selections:
2.0V and 4.1V.
The A/D Converter can uniquely operate while the
device is in Sleep mode. To operate in Sleep, the A/D
conversion clock must be derived from the A/D’s
internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF (PIR1<6>), is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure 23-4.
DS39977F-page 364
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