PIC18F45K80-I Datasheet, PDF (565/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
TABLE 31-10: CLKO AND I/O TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
150 TadV2alL Address Out Valid to ALE 
(address setup time)
0.25 TCY – 10
—
—
ns
151 TalL2adl ALE  to Address Out Invalid
(address hold time)
5
—
—
ns
155 TalL2oeL ALE to OE 
10
0.125 TCY
—
ns
160 TadZ2oeL AD High-Z to OE (bus release to OE)
0
—
—
ns
161 ToeH2adD OE  to AD Driven
0.125 TCY – 5
—
—
ns
162 TadV2oeH LS Data Valid before OE (data setup time)
20
—
—
ns
163 ToeH2adl OE  to Data In Invalid (data hold time)
0
—
—
ns
164 TalH2alL ALE Pulse Width
—
0.25 TCY
—
ns
165 ToeL2oeH OE Pulse Width
0.5 TCY – 5 0.5 TCY
—
ns
166 TalH2alH ALE  to ALE  (cycle time)
—
TCY
—
ns
167 Tacc
Address Valid to Data Valid
0.75 TCY – 25
—
—
ns
168 Toe
OE  to Data Valid
—
0.5 TCY – 25 ns
169 TalL2oeH ALE to OE 
0.625 TCY – 10
—
0.625 TCY + 10 ns
171 TalH2csL Chip Enable Active to ALE 
0.25 TCY – 20
—
—
ns
171A TubL2oeH AD Valid to Chip Enable Active
—
—
10
ns
FIGURE 31-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
I/O pins
33
32
30
34
31
34
Note: Refer to Figure 31-3 for load conditions.
 2010-2012 Microchip Technology Inc.
DS39977F-page 565