PIC18F45K80-I Datasheet, PDF (466/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 28-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-0
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB: Boot Block Code Protection bit
1 = Boot block is not code-protected⁽¹⁾
0 = Boot block is code-protected⁽¹⁾
Unimplemented: Read as ‘0’
Note 1: For the memory size of the blocks, see Figure 28-6. The boot block size changes with BBSIZ0.
DS39977F-page 466
 2010-2012 Microchip Technology Inc.