PIC18F45K80-I Datasheet, PDF (78/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power-Managed
Mode
Clock Source⁽⁵⁾
Exit Delay
Clock Ready
Status Bits
LP, XT, HS
HSPLL
OSTS
PRI_IDLE mode
EC, RC
HF-INTOSC⁽²⁾
TCSD⁽¹⁾
HFIOFS
MF-INTOSC⁽²⁾
MFIOFS
LF-INTOSC
None
SEC_IDLE mode
SOSC
TCSD⁽¹⁾
SOSCRUN
HF-INTOSC⁽²⁾
HFIOFS
RC_IDLE mode
MF-INTOSC⁽²⁾
TCSD⁽¹⁾
MFIOFS
LF-INTOSC
None
LP, XT, HS
TOST⁽³⁾
Sleep mode
HSPLL
EC, RC
HF-INTOSC⁽²⁾
TOST + t_rc⁽³⁾
TCSD⁽¹⁾
OSTS
HFIOFS
MF-INTOSC⁽²⁾
TIOBST⁽⁴⁾
MFIOFS
LF-INTOSC
None
Note 1: TCSD (Parameter 38, Table 31-11) is a required delay when waking from Sleep and all Idle modes, and
runs concurrently with any other required delays (see Section 4.4 “Idle Modes”).
2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
3: TOST is the Oscillator Start-up Timer (Parameter 32, Table 31-11). TRC is the PLL Lock-out Timer
(Parameter F12, Table 31-7); it is also designated as TPLL.
4: Execution continues during TIOBST (Parameter 39, Table 31-11), the INTOSC stabilization period.
5: The clock source is dependent upon the settings of the SCSx (OSCCON<1:0>), IRCFx (OSCCON<6:4>)
and FOSCx (CONFIG1H<3:0>) bits.
DS39977F-page 78
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