PIC18F45K80-I Datasheet, PDF (330/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
21.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 21-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 21-34).
FIGURE 21-33:
SDA
SCL
PEN
BCLIF
P
SSPIF
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
FIGURE 21-34:
SDA
SCL
PEN
BCLIF
P
SSPIF
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
Assert SDA
SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
DS39977F-page 330
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