PIC18F45K80-I Datasheet, PDF (454/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
27.15.1 INTERRUPT CODE BITS
To simplify the interrupt handling process in user firm-
ware, the ECAN module encodes a special set of bits. In
Mode 0, these bits are ICODE<3:1> in the CANSTAT
register. In Mode 1 and 2, these bits are EICODE<4:0> in
the CANSTAT register. Interrupts are internally prioritized
such that the higher priority interrupts are assigned lower
values. Once the highest priority interrupt condition has
been cleared, the code for the next highest priority inter-
rupt that is pending (if any) will be reflected by the ICODE
bits (see Table 27-4). Note that only those interrupt
sources that have their associated interrupt enable bit set
will be reflected in the ICODE bits.
In Mode 2, when a receive message interrupt occurs,
the EICODE bits will always consist of ‘10000’. User
firmware may use FIFO Pointer bits to actually access
the next available buffer.
27.15.2 TRANSMIT INTERRUPT
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. In Mode 0, there are separate interrupt enable/
disable and flag bits for each of the three dedicated trans-
mit buffers. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU, resetting the TXBnIF bit to a ‘0’. In Mode 1 and 2,
all transmit buffers share one interrupt enable/disable bit
and one flag bit. In Mode 1 and 2, TXBnIE in PIE5 and
TXBnIF in PIR5 indicate when a transmit buffer has com-
pleted transmission of its message. TXBnIF, TXBnIE and
TXBnIP in PIR5, PIE5 and IPR5, respectively, are not
used in Mode 1 and 2. Individual transmit buffer interrupts
can be enabled or disabled by setting or clearing TXBnIE
and B0IE register bits. When a shared interrupt occurs,
user firmware must poll the TXREQ bit of all transmit
buffers to detect the source of interrupt.
27.15.3 RECEIVE INTERRUPT
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the End-of-Frame (EOF) field.
In Mode 0, the RXBnIF bit is set to indicate the source
of the interrupt. The interrupt is cleared by the MCU,
resetting the RXBnIF bit to a ‘0’.
In Mode 1 and 2, all receive buffers share RXBnIE,
RXBnIF and RXBnIP in PIE5, PIR5 and IPR5, respec-
tively. Bits, RXBnIE, RXBnIF and RXBnIP, are not
used. Individual receive buffer interrupts can be con-
trolled by the TXBnIE and BIE0 registers. In Mode 1,
when a shared receive interrupt occurs, user firmware
must poll the RXFUL bit of each receive buffer to detect
the source of interrupt. In Mode 2, a receive interrupt
indicates that the new message is loaded into FIFO.
FIFO can be read by using FIFO Pointer bits, FP.
TABLE 27-4: VALUES FOR ICODE<2:0>
ICODE
<2:0>
Interrupt
Boolean Expression
000 None ERR•WAK•TX0•TX1•TX2•RX0•RX1
001 Error ERR
010 TXB2 ERR•TX0•TX1•TX2
011 TXB1 ERR•TX0•TX1
100 TXB0 ERR•TX0
101 RXB1 ERR•TX0•TX1•TX2•RX0•RX1
110 RXB0 ERR•TX0•TX1•TX2•RX0
111 Wake on ERR•TX0•TX1•TX2•RX0•RX1•WAK
Interrupt
Legend:
ERR = ERRIF * ERRIE
TX0 = TXB0IF * TXB0IE
TX1 = TXB1IF * TXB1IE
TX2 = TXB2IF * TXB2IE
RX0 = RXB0IF * RXB0IE
RX1 = RXB1IF * RXB1IE
WAK = WAKIF * WAKIE
27.15.4 MESSAGE ERROR INTERRUPT
When an error occurs during transmission or reception
of a message, the message error flag, IRXIF, will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
27.15.5 BUS ACTIVITY WAKE-UP
INTERRUPT
When the PIC18F66K80 family devices are in Sleep
mode and the bus activity wake-up interrupt is enabled,
an interrupt will be generated and the WAKIF bit will be
set when activity is detected on the CAN bus. This
interrupt causes the PIC18F66K80 family devices to
exit Sleep mode. The interrupt is reset by the MCU,
clearing the WAKIF bit.
27.15.6 ERROR INTERRUPT
When the CAN module error interrupt (ERRIE in PIE5)
is enabled, an interrupt is generated if an overflow con-
dition occurs, or if the error state of the transmitter or
receiver has changed. The error flags in COMSTAT will
indicate one of the following conditions.
DS39977F-page 454
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