PIC18F45K80-I Datasheet, PDF (361/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
23.2.2 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is where the 12-bit
A/D result and extended sign bits (ADSGNx) are
loaded at the completion of a conversion. This register
pair is 16 bits wide. The A/D module gives the flexibility
of left or right justifying the 12-bit result in the 16-bit
result register. The A/D Format Select bit (ADFM) con-
trols this justification.
Figure 23-3 shows the operation of the A/D result
justification and the location of the sign bit (ADSGNx).
The extended sign bits allow for easier 16-bit math to
FIGURE 23-3:
A/D RESULT JUSTIFICATION
be performed on the result. The results are
represented as a two's compliment binary value. This
means that when sign bits and magnitude bits are
considered together in right justification, the ADRESH
and ADRESL registers can be read as a single signed
integer value.
When the A/D Converter is disabled, these 8-bit
registers can be used as two general purpose
registers.
Left Justified
ADFM = 0
12-Bit Result
Right Justified
ADFM = 1
ADRESH
ADRESL
ADRESH
ADRESL
Result bits
ADSGN bit
Hex
0xFFF0
0xFFE0
…
0x0020
0x0010
0x0000
0xFFFF
0xFFEF
…
0x001F
0x000F
Two’s Complement Example Results Number Line
Left Justified
Right Justified
Decimal
4095
4094
…
2
1
0
-1
-2
…
-4095
-4096
Hex
0x0FFF
0x0FFE
…
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
…
0xF001
0xF000
Decimal
4095
4094
…
2
1
0
-1
-2
…
-4095
-4096
 2010-2012 Microchip Technology Inc.
DS39977F-page 361