PIC18F45K80-I Datasheet, PDF (171/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
11.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to seven ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register, writes
to the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (putting the corresponding output driver in
a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., put
the contents of the corresponding LAT bit on the
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
WR LAT
or PORT
WR TRIS
RD TRIS
D
Q
CKx
Data Latch
D
Q
CKx
TRIS Latch
I/O Pin⁽¹⁾
Input
Buffer
Q
D
RD PORT
ENEN
Note 1: I/O pins have diode protection to VDD and VSS.
11.1 I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
All of the digital ports are 5.5V input tolerant. The
analog ports have the same tolerance, having clamping
diodes implemented internally.
11.1.1 PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary, according to the pins’ grouping to meet the needs
for a variety of applications. In general, there are two
classes of output pins, in terms of drive capability:
• Outputs that are designed to drive higher current
loads, such as LEDs:
- PORTA
– PORTB
- PORTC
• Outputs with lower drive levels, but capable of
driving normal digital circuit loads with a high input
impedance. Able to drive LEDs, but only those
with smaller current requirements:
- PORTD⁽¹⁾
– PORTE⁽¹⁾
- PORTF⁽²⁾
– PORTG⁽²⁾
Note 1: These ports are not available on 28-pin
devices.
2: These ports are not available on 28-pin
or 40/44-pin devices
For more details, see “Absolute Maximum Ratings” in
Section 31.0 “Electrical Characteristics”.
11.1.2 PULL-UP CONFIGURATION
Five of the I/O ports (PORTB, PORTD, PORTE,
PORTF and PORTG) implement configurable weak
pull-ups on all pins. These are internal pull-ups that
allow floating digital input signals to be pulled to a
consistent level without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU, RFPU and RGPU (PADCFG1<7:4>) for the
other ports.
Additionally, the PORTB pull-up resistors can be
enabled individually using the WPUB register. Each bit
in the register corresponds to a bit on PORTB.
 2010-2012 Microchip Technology Inc.
DS39977F-page 171