PIC18F45K80-I Datasheet, PDF (398/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
REGISTER 27-3: ECANCON: ENHANCED CAN CONTROL REGISTER
R/W-0
MDSEL1⁽¹⁾
bit 7
R/W-0
MDSEL0⁽¹⁾
R/W-0
FIFOWM⁽²⁾
R/W-1
EWIN4
R/W-0
EWIN3
R/W-0
EWIN2
R/W-0
EWIN1
R/W-0
EWIN0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4-0
MDSEL<1:0>: Mode Select bits⁽¹⁾
00 = Legacy mode (Mode 0, default)
01 = Enhanced Legacy mode (Mode 1)
10 = Enhanced FIFO mode (Mode 2)
11 = Reserved
FIFOWM: FIFO High Water Mark bit⁽²⁾
1 = Will cause FIFO interrupt when one receive buffer remains
0 = Will cause FIFO interrupt when four receive buffers remain⁽³⁾
EWIN<4:0>: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into Access Bank addresses, 0F60-0F6Dh. The
exact group of registers to map is determined by the binary value of these bits.
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3
00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010 = Acceptance Filter Masks, Error and Interrupt Control
00011 = Transmit Buffer 0
00100 = Transmit Buffer 1
00101 = Transmit Buffer 2
00110 = Acceptance Filters 6, 7, 8
00111 = Acceptance Filters 9, 10, 11
01000 = Acceptance Filters 12, 13, 14
01001 = Acceptance Filter 15
01010-01110 = Reserved
01111 = RXINT0, RXINT1
10000 = Receive Buffer 0
10001 = Receive Buffer 1
10010 = TX/RX Buffer 0
10011 = TX/RX Buffer 1
10100 = TX/RX Buffer 2
10101 = TX/RX Buffer 3
10110 = TX/RX Buffer 4
10111 = TX/RX Buffer 5
11000-11111 = Reserved
Note 1:
2:
3:
These bits can only be changed in Configuration mode. See Register 27-1 to change to Configuration mode.
This bit is used in Mode 2 only.
If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.
DS39977F-page 398
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