PIC18F45K80-I Datasheet, PDF (83/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
5.5 Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXKXX Flash devices, the device Configura-
tion registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow reg-
isters. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>) being
set to ‘0’.
This bit does not change for any other Reset event. A
CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6 Device Reset Timers
PIC18F66K80 family devices incorporate three sepa-
rate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.6.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F66K80
family devices is an 11-bit counter which uses the
INTOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC Parameter 33 for
details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
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DS39977F-page 83