PIC18F45K80-I Datasheet, PDF (333/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
22.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USARTx modules implement additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN/J2602 bus) systems.
All members of the PIC18F66K80 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
• Synchronous – Slave (half duplex) with selectable
clock polarity
The pins of EUSART1 and EUSART2 are multiplexed
with the functions with the following ports, depending
on the device pin count. See Table 22-1.
TABLE 22-1: CONFIGURING EUSARTx PINS⁽¹⁾
Pin
Count
Port
EUSART1
Pins
Port
EUSART2
Pins
28-pin PORTC
RC6/TX1/CK1 and
RC7/RX1/DT1
PORTB
RB6/PGC/TX2/CK2/KBI2 and
RB7/PGD/T3G/RX2/DT2/KBI3
40/44-pin PORTC
RC6/TX1/CK1 and
RC7/RX1/DT1
PORTD
RD6/TX2/CK2/P1C/PSP6 and
RD7/RX2/DT2/P1D/PSP7
64-pin PORTG
RG3/TX1/CK1 and
RG0/RX1/DT1
PORTE
RE7/TX2/CK2 and RE6/RX2/DT2
Note 1: The EUSARTx control will automatically reconfigure the pin from input to output as needed.
In order to configure the pins as an EUSARTx:
• For EUSART1:
- SPEN (RCSTA1<7>) must be set (= 1)
- TRISx<x> must be set (= 1)
- For Asynchronous and Synchronous Master
modes, TRISx<x> must be cleared (= 0)
- For Synchronous Slave mode, TRISx<x>
must be set (= 1)
• For EUSART2:
- SPEN (RCSTA2<7>) must be set (= 1)
- TRISx<x> must be set (= 1)
- For Asynchronous and Synchronous Master
modes, TRISx<x> must be cleared (= 0)
- For Synchronous Slave mode, TRISx<x>
must be set (= 1)
 2010-2012 Microchip Technology Inc.
DS39977F-page 333