PIC18F45K80-I Datasheet, PDF (179/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
TABLE 11-3: PORTB FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O I/O Type
Description
RB4/AN9/C2INA/
ECCP1/P1A/CTPLS/
KBI0
RB4
AN9
0
O
DIG LATB<4> data output.
1
I
ST PORTB<4> data input; weak pull-up when RBPU bit is cleared.
1
I
ANA A/D Input Channel 9 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
C2INA⁽¹⁾
2
I
ANA Comparator 2 Input A.
ECCP1⁽¹⁾
0
O
DIG ECCP1 compare output and ECCP1 PWM output. Takes priority
over port data.
1
I
ST ECCP1 capture input.
P1A⁽¹⁾
0
O
DIG ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority
over port data.
CTPLS
x
O
DIG CTMU pulse generator output.
KBI0
1
I
ST Interrupt-on-pin change.
RB5/T0CKI/T3CKI/
CCP5/KBI1
RB5
0
O
DIG LATB<5> data output.
1
I
ST PORTB<5> data input; weak pull-up when RBPU bit is cleared.
T0CKI⁽³⁾
x
I
ST Timer0 clock input.
T3CKI⁽⁴⁾
x
I
ST Timer3 clock input.
CCP5
0
O
DIG CCP5 compare/PWM output. Takes priority over port data.
1
I
ST CCP5 capture input.
KBI1
1
I
ST Interrupt-on-pin change.
RB6/PGC/TX2/CK2/
KBI2
RB6
0
O
DIG LATB<6> data output.
1
I
ST PORTB<6> data input; weak pull-up when RBPU bit is cleared.
PGC
x
I
ST Serial execution (ICSP™) clock input for ICSP and ICD operation.
TX2⁽¹⁾
0
O
DIG Asynchronous serial data output (EUSARTx module); takes priority
over port data.
CK2⁽¹⁾
0
O
DIG Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1
I
ST Synchronous serial clock input (EUSARTx module); user must
configure as an input.
KBI2
1
I
ST Interrupt-on-pin change.
RB7/PGD/T3G/RX2/
DT2/KBI3
RB7
0
O
DIG LATB<7> data output.
1
I
ST PORTB<7> data input; weak pull-up when RBPU bit is cleared.
PGD
x
O
DIG Serial execution data output for ICSP and ICD operation.
x
I
ST Serial execution data input for ICSP and ICD operation.
T3G
x
I
ST Timer3 external clock gate input.
RX2⁽¹⁾
1
I
ST Asynchronous serial receive data input (EUSARTx module).
DT2⁽¹⁾
1
O
DIG Synchronous serial data output (AUSART module); takes priority
over port data.
1
I
ST Synchronous serial data input (AUSART module); user must
configure as an input.
KBI3
1
I
ST Interrupt-on-pin change.
Legend:
Note 1:
2:
3:
4:
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This pin assignment is only available for 28-pin devices (PIC18F2XK80).
This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for
T3CKI for 64-pin devices when T3CKMX is cleared.
 2010-2012 Microchip Technology Inc.
DS39977F-page 179