PIC18F45K80-I Datasheet, PDF (472/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
28.2 Watchdog Timer (WDT)
For the PIC18F66K80 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCFx bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
WDT BLOCK DIAGRAM
The WDT can be operated in one of four modes as
determined by WDTEN<1:0> (CONFIG2H<1:0>. The
four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control,
SWDTEN (WDTCON<0>)
• WDT
- Enabled during normal operation
- Disabled during Sleep
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCFx bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
WDT Enabled,
SWDTEN Disabled
WDT Controlled with
SWDTEN bit Setting
WDT Enabled only while
Device Active, Disabled
WDT Disabled in Hardware,
SWDTEN Disabled
WDTEN1
WDTEN0
INTOSC Source
Change on IRCFx bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
WDT Counter
128
Programmable Postscaler ^Reset
1:1 to 1:1,048,576
4
Wake-up from
Power-Manage
Modes
WDT
Reset
SWDTEN
WDTEN<1:0>
INTOSC Source
Enable WDT
DS39977F-page 472
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