PIC18F45K80-I Datasheet, PDF (379/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
24.6 Comparator Interrupts
The comparator interrupt flag is set whenever any of
the following occurs:
• Low-to-high transition of the comparator output
• High-to-low transition of the comparator output
• Any change in the comparator output
The comparator interrupt selection is done by the
EVPOL<1:0> bits in the CMxCON register
(CMxCON<4:3>).
In order to provide maximum flexibility, the output of the
comparator may be inverted using the CPOL bit in the
CMxCON register (CMxCON<5>). This is functionally
identical to reversing the inverting and non-inverting
inputs of the comparator for a particular mode.
An interrupt is generated on the low-to-high or high-to-
low transition of the comparator output. This mode of
interrupt generation is dependent on EVPOL<1:0> in
the CMxCON register. When EVPOL<1:0> = 01 or 10,
the interrupt is generated on a low-to-high or high-to-
low transition of the comparator output. Once the
interrupt is generated, it is required to clear the interrupt
flag by software.
When EVPOL<1:0> = 11, the comparator interrupt flag
is set whenever there is a change in the output value of
either comparator. Software will need to maintain
information about the status of the output bits, as read
from CMSTAT<7:6>, to determine the actual change
that occurred.
The CMPxIF<2:0> (PIR4<5:4) bits are the Comparator
Interrupt Flags. The CMPxIF bits must be reset by
clearing them. Since it is also possible to write a ‘1’ to
this register, a simulated interrupt may be initiated.
Table 24-2 shows the interrupt generation with respect
to comparator input voltages and EVPOL bit settings.
Both the CMPxIE bits (PIE4<5:4>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMPxIF bits will still be set if an interrupt
condition occurs.
A simplified diagram of the interrupt section is shown in
Figure 24-3.
Note: CMPxIF will not be set when
EVPOL<1:0> = 00.
TABLE 24-2:
CPOL
0
1
COMPARATOR INTERRUPT GENERATION
EVPOL<1:0>
Comparator
Input Change
CxOUT Transition
VIN+ > VIN-
Low-to-High
00
VIN+ < VIN-
High-to-Low
VIN+ > VIN-
Low-to-High
01
VIN+ < VIN-
High-to-Low
VIN+ > VIN-
Low-to-High
10
VIN+ < VIN-
High-to-Low
VIN+ > VIN-
Low-to-High
11
VIN+ < VIN-
High-to-Low
VIN+ > VIN-
High-to-Low
00
VIN+ < VIN-
Low-to-High
VIN+ > VIN-
High-to-Low
01
VIN+ < VIN-
Low-to-High
VIN+ > VIN-
High-to-Low
10
VIN+ < VIN-
Low-to-High
VIN+ > VIN-
High-to-Low
11
VIN+ < VIN-
Low-to-High
Interrupt
Generated
No
No
Yes
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
 2010-2012 Microchip Technology Inc.
DS39977F-page 379