PIC18F45K80-I Datasheet, PDF (111/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
6.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
all of Bank 15 (F00h to FFFh) and the top part of
Bank 14 (EF4h to EFFh).
A list of these registers is given in Table 6-1 and
Table 6-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY
Addr.
Name
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0⁽¹⁾
POSTINC0⁽¹⁾
POSTDEC0⁽¹⁾
PREINC0⁽¹⁾
PLUSW0⁽¹⁾
FSR0H
FSR0L
WREG
INDF1⁽¹⁾
POSTINC1⁽¹⁾
POSTDEC1⁽¹⁾
PREINC1⁽¹⁾
PLUSW1⁽¹⁾
FSR1H
FSR1L
BSR
Addr.
Name
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
INDF2⁽¹⁾
POSTINC2⁽¹⁾
POSTDEC2⁽¹⁾
PREINC2⁽¹⁾
PLUSW2⁽¹⁾
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—⁽²⁾
OSCCON
OSCCON2
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Addr.
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
Name
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
TXSTA2
BAUDCON2
IPR4
PIR4
PIE4
CVRCON
CMSTAT
TMR3H
TMR3L
T3CON
T3GCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
T1GCON
PR4
HLVDCON
BAUDCON1
RCSTA2
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
Addr.
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
PSTR1CON
OSCTUNE
REFOCON
CCPTMRS
TRISG⁽³⁾
TRISF⁽³⁾
TRISE⁽⁴⁾
TRISD⁽⁴⁾
TRISC
TRISB
TRISA
ODCON
SLRCON
LATG⁽³⁾
LATF⁽³⁾
LATE⁽⁴⁾
LATD⁽⁴⁾
LATC
LATB
LATA
T4CON
TMR4
PORTG⁽³⁾
PORTF⁽³⁾
PORTE
PORTD⁽⁴⁾
PORTC
PORTB
PORTA
Addr. Name
F7Fh EECON1
F7Eh EECON2
F7Dh SPBRGH1
F7Ch SPBRGH2
F7Bh SPBRG2
F7Ah RCREG2
F79h TXREG2
F78h IPR5
F77h PIR5
F76h PIE5
F75h EEADRH
F74h EEADR
F73h EEDATA
F72h ECANCON
F71h COMSTAT
F70h CIOCON
F6Fh CANCON
F6Eh CANSTAT
F6Dh RXB0D7
F6Ch RXB0D6
F6Bh RXB0D5
F6Ah RXB0D4
F69h RXB0D3
F68h RXB0D2
F67h RXB0D1
F66h RXB0D0
F65h RXB0DLC
F64h RXB0EIDL
F63h RXB0EIDH
F62h RXB0SIDL
F61h RXB0SIDH
F60h RXB0CON
Addr. Name
F5Fh CM1CON⁽⁵⁾
F5Eh CM2CON⁽⁵⁾
F5Dh ANCON0⁽⁵⁾
F5Ch ANCON1⁽⁵⁾
F5Bh WPUB⁽⁵⁾
F5Ah IOCB⁽⁵⁾
F59h PMD0⁽⁵⁾
F58h PMD1⁽⁵⁾
F57h PMD2⁽⁵⁾
F56h PADCFG1⁽⁵⁾
F55h CTMUCONH⁽⁵⁾
F54h CTMUCONL⁽⁵⁾
F53h CTMUICONH⁽⁵⁾
F52h CCPR2H⁽⁵⁾
F51h CCPR2L⁽⁵⁾
F50h CCP2CON^(4,5)
F4Fh CCPR3H^(4,5)
F4Eh CCPR3L^(4,5)
F4Dh CCP3CON⁽⁵⁾
F4Ch CCPR4H⁽⁵⁾
F4Bh CCPR4L⁽⁵⁾
F4Ah CCP4CON⁽⁵⁾
F49h CCPR5H⁽⁵⁾
F48h CCPR5L⁽⁵⁾
F47h CCP5CON⁽⁵⁾
F46h PSPCON^(4,5)
F45h MDCON^(3,5)
F44h MDSRC^(3,5)
F43h MDCARH^(3,5)
F42h MDCARL^(3,5)
F41h
—⁽²⁾
F40h
—⁽²⁾
Note 1:
2:
3:
4:
5:
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is only available on devices with 64 pins.
This register is not available on devices with 28 pins.
Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must
always load the proper BSR value.
 2010-2012 Microchip Technology Inc.
DS39977F-page 111