PIC18F45K80-I Datasheet, PDF (284/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 20-16:
STRA
P1A Signal
CCP1M1
Port Data
STRB
SIMPLIFIED STEERING
BLOCK DIAGRAM^(1,2)
Output Pin
1
0
TRIS
CCP1M0
Port Data
STRC
1
Output Pin
0
TRIS
CCP1M1
Port Data
STRD
1
Output Pin
0
TRIS
CCP1M0
1
Output Pin
Port Data
0
TRIS
Note 1:
2:
Port outputs are configured as displayed when
the CCP1CON register bits, P1M<1:0> = 00
and CCP1M<3:2> = 11.
Single PWM output requires setting at least
one of the STR<D:A> bits.
20.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTR1CON register gives the
user two choices for when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTR1CON register. In this case, the out-
put signal at the P1<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 20-17 and 20-18 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 20-17:
PWM
STR<D:A>
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
PWM Period
P1<D:A>
Port Data
P1n = PWM
Port Data
FIGURE 20-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
PWM
STR<D:A>
P1<D:A>
Port Data
P1n = PWM
Port Data
DS39977F-page 284
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