PIC18F45K80-I Datasheet, PDF (382/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 25-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ ^{CVRSS = 1}
AVDD _{CVRSS = 0}
CVR<4:0>
CVREN
R
R
R
R
32 Steps
CVREF
R
R
R
VREF-
CVRSS = 1
CVRSS = 0
25.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 25-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 31.0 “Electrical Characteristics”.
25.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
25.4 Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RF5 pin by clearing
bit, CVROE (CVRCON<6>).
25.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA0 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA0 when it is configured as a digital input will
increase current consumption. Connecting RA0 as a
digital output with CVRSS enabled will also increase
current consumption.
The RA0 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 25-2 shows an example buffering technique.
DS39977F-page 382
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