PIC18F45K80-I Datasheet, PDF (173/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN and nanoWatt XLP Technology

PIC18F66K80 FAMILY
11.1.3 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the ODCON
register.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 11-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
FIGURE 11-2:
USING THE OPEN-DRAIN
OUTPUT (USARTx SHOWN
AS EXAMPLE)
3.3V
+5V
PIC18F66K80
VDD
TXX ^3.3V
5V
(at logic ‘1’)
REGISTER 11-3: ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER
R/W-0
SSPOD
bit 7
R/W-0
CCP5OD
R/W-0
CCP4OD
R/W-0
CCP3OD
R/W-0
CCP2OD
R/W-0
CCP1OD
R/W-0
U2OD
R/W-0
U1OD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSPOD: SPI Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 6
CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 5
CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 4
CCP3OD: CCP3 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 3
CCP2OD: CCP2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 2
CCP1OD: CCP1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 1
U2OD: UART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0
U1OD: UART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
 2010-2012 Microchip Technology Inc.
DS39977F-page 173