HD6473032F Datasheet, PDF (9/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Section 8 16-Bit Integrated Timer Unit (ITU)..................................................... 169
8.1 Overview ........................................................................................................................ 169
8.1.1 Features........................................................................................................... 169
8.1.2 Block Diagrams .............................................................................................. 172
8.1.3 Input/Output Pins............................................................................................ 177
8.1.4 Register Configuration.................................................................................... 178
8.2 Register Descriptions...................................................................................................... 181
8.2.1 Timer Start Register (TSTR) .......................................................................... 181
8.2.2 Timer Synchro Register (TSNC) .................................................................... 182
8.2.3 Timer Mode Register (TMDR)....................................................................... 184
8.2.4 Timer Function Control Register (TFCR) ...................................................... 187
8.2.5 Timer Output Master Enable Register (TOER) .............................................. 189
8.2.6 Timer Output Control Register (TOCR)......................................................... 192
8.2.7 Timer Counters (TCNT) ................................................................................. 193
8.2.8 General Registers (GRA, GRB) ..................................................................... 194
8.2.9 Buffer Registers (BRA, BRB) ........................................................................ 195
8.2.10 Timer Control Registers (TCR) ...................................................................... 196
8.2.11 Timer I/O Control Register (TIOR)................................................................ 198
8.2.12 Timer Status Register (TSR)........................................................................... 200
8.2.13 Timer Interrupt Enable Register (TIER)......................................................... 203
8.3 CPU Interface ................................................................................................................. 205
8.3.1 16-Bit Accessible Registers............................................................................ 205
8.3.2 8-Bit Accessible Registers.............................................................................. 207
8.4 Operation ........................................................................................................................ 209
8.4.1 Overview......................................................................................................... 209
8.4.2 Basic Functions............................................................................................... 210
8.4.3 Synchronization .............................................................................................. 220
8.4.4 PWM Mode .................................................................................................... 222
8.4.5 Reset-Synchronized PWM Mode ................................................................... 226
8.4.6 Complementary PWM Mode.......................................................................... 229
8.4.7 Phase Counting Mode..................................................................................... 239
8.4.8 Buffering......................................................................................................... 241
8.4.9 ITU Output Timing......................................................................................... 248
8.5 Interrupts ........................................................................................................................ 250
8.5.1 Setting of Status Flags .................................................................................... 250
8.5.2 Clearing of Status Flags.................................................................................. 252
8.5.3 Interrupt Sources............................................................................................. 253
8.6 Usage Notes .................................................................................................................... 254