HD6473032F Datasheet, PDF (569/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

Reset in T₂ State: Figure D-2 is a timing diagram for the case in which RES goes low during the
T₂ state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
The same timing applies when a reset occurs during a wait state (T_W).
ø
RES
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
Access to external address
T₁
T₂
T₃
H'000000
High impedance
High impedance
Figure D-2 Reset during Memory Access (Reset during T₂ State)
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