HD6473032F Datasheet, PDF (11/572 Pages) Hitachi Semiconductor – Hitachi Microcomputer

10.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 307
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 308
10.4 Interrupts ........................................................................................................................ 309
10.5 Usage Notes .................................................................................................................... 309
Section 11 Serial Communication Interface........................................................... 311
11.1 Overview ........................................................................................................................ 311
11.1.1 Features........................................................................................................... 311
11.1.2 Block Diagram................................................................................................ 313
11.1.3 Input/Output Pins............................................................................................ 314
11.1.4 Register Configuration.................................................................................... 314
11.2 Register Descriptions...................................................................................................... 315
11.2.1 Receive Shift Register (RSR) ......................................................................... 315
11.2.2 Receive Data Register (RDR)......................................................................... 315
11.2.3 Transmit Shift Register (TSR)........................................................................ 316
11.2.4 Transmit Data Register (TDR) ....................................................................... 316
11.2.5 Serial Mode Register (SMR) .......................................................................... 317
11.2.6 Serial Control Register (SCR) ........................................................................ 321
11.2.7 Serial Status Register (SSR) ........................................................................... 325
11.2.8 Bit Rate Register (BRR) ................................................................................. 329
11.3 Operation ........................................................................................................................ 338
11.3.1 Overview......................................................................................................... 338
11.3.2 Operation in Asynchronous Mode.................................................................. 340
11.3.3 Multiprocessor Communication ..................................................................... 349
11.3.4 Synchronous Operation .................................................................................. 356
11.4 SCI Interrupts.................................................................................................................. 365
11.5 Usage Notes .................................................................................................................... 366
Section 12 A/D Converter............................................................................................ 371
12.1 Overview ........................................................................................................................ 371
12.1.1 Features........................................................................................................... 371
12.1.2 Block Diagram................................................................................................ 372
12.1.3 Input Pins ........................................................................................................ 373
12.1.4 Register Configuration.................................................................................... 374
12.2 Register Descriptions...................................................................................................... 375
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 375
12.2.2 A/D Control/Status Register (ADCSR) .......................................................... 376
12.2.3 A/D Control Register (ADCR) ....................................................................... 379
12.3 CPU Interface ................................................................................................................. 380
12.4 Operation ........................................................................................................................ 381
12.4.1 Single Mode (SCAN = 0) ............................................................................... 381